FPGA Implementation of Selective Harmonic Elimination Controlled Asymmetrical Cascaded Nine Levels Inverter Using Newton Raphson Algorithm

Asymmetrical structure is used to reduce the number of bridges and gate drive circuits and DC sources. This structure therefore provides the capability to produce higher voltages at higher speeds with low switching frequency which has inherent low switching losses and high converter efficiency. Newton Raphson (N-R) algorithm is investigated for the selective harmonic elimination (SHE) to calculate switching angles for a range of variation for the modulation rate ‘r’ for an asymmetrical cascaded multilevel inverter control. Based on simulation studies, performance of the proposed algorithm for a nine levels asymmetrical cascaded H-bridge inverter, is evaluated and experimentally tested on an prototype using FPGA to implement SHE based on NR algorithm. Keywords— Asymmetrical CHB multilevel inverter, Newton Raphson algorithm, Switching angles, SHE, THD, FPGA.